The race is on to make advanced packaging less expensive than shrinking everything down onto the same die—much less expensive, in fact.
Following several years of speculation and rather shaky market predictions at the beginning of this decade, packaging houses and foundries spent the last four years proving that packaging really does provide a viable alternative to shrinking die in terms of performance, power and form factor. Apple’s adoption of TSMC’s Integrated Fan-Out packaging was the crowning achievement, because Apple and Samsung phones have the highest single-chip volume production on the planet. But there have been many less-obvious examples of advanced packaging in use for AMD graphics, Cisco and Huawei networking chips, and some very high-performance server chips.
Having proved its claims in mass production and yield, the packaging industry is now shifting into the next phase of its development effort. It is working to cut the cost of advanced packaging to make it price-competitive with single-chip solutions.
First, it has adopted a business plan that is all-inclusive. Rather than exclude any chip technology, packaging can be adapted to incorporate almost anything. It can include gate-all-around FETs developed at 5nm or 3nm, as well as a 90nm SerDes and a number of accelerators and memory types and I/O IP that was developed at 45nm.
IBM pioneered this business strategy in the technology world in the mid-1990s after recognizing that it would never be able to unseat Microsoft Windows with the OS/2 desktop operating system that IBM had co-developed with Microsoft. Rather than fighting Microsoft head-on, Big Blue adopted a strategy that attempted to marginalize Windows. In IBM’s marketing pitches, Windows was just one more operating system, and IBM subsequently began sinking money into commercializing Linux.
While the success of this approach isn’t obvious on the desktop, it’s very clear in the datacenter. IBM really never thought the PC would amount to much, and for IBM it’s arguable whether it ever proved to be more than a stepping stone. The company sold off its PC group to Lenovo in 2004 for $1.75 billion, in part because it gave IBM stronger footing in what was then considered the next big growth market—China.
Second, two of the biggest names in processors, Intel and Samsung, have developed inexpensive bridge technology to cut the cost and speed up multi-die packaging. The biggest complaint about silicon interposers is the cost of the interposer itself, which essentially adds another chip between two or more other chips. By adding an inexpensive bridge, either after the chips are placed in a package (Intel), or in the redistribution layer (Samsung), performance can be improved sufficiently to support a multi-chip business model. Moreover, by architecting these devices with throughput in mind—shrinking distances between components such as logic and memory and accelerator technology—the amount of power necessary to drive signals can be reduced, as well.
The third step, which is now being developed by virtually every company seriously interested in advanced packaging, is a panel-based approach. The argument for panel-based packaging is roughly similar to the economics for 450mm wafers, only there are no limitations on which chips can leverage this approach. The scaling benefit isn’t about specific chips produced by the billions of units. It’s about heterogeneous packages. And the more packages that can be created on a single substrate, the greater the cost savings (providing yields are sufficient, of course). The fact that there is no agreed-upon panel size yet is problematic, but it’s also a testament to how many companies are working on driving down the cost of fan-outs and system-in-package.
The next steps will fall into line from here:
• Establish standards for panel sizes, thicknesses and tolerances;
The hype cycle is over. Packaging is now a real and growing part of the chip ecosystem. The question now is how that will impact other parts of the ecosystem and research in areas that require huge volumes to recoup R&D costs.
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